As is well known, microprograms generally have branch decision points where selections between alternate microinstruction paths are made. Typically, the selection process at a decision point involves directing the controller to execute one of two different microprogram sequences as a result of a test. For example, if the test is FALSE the next microinstruction is fetched using the next sequential microinstruction address; however, if the test is TRUE, the next microinstruction is fetched using the branch or jump address field of the present microinstruction. Since selection of the correct path can not be determined until the test results are valid, the fetching of the next microinstruction is delayed.
The microinstruction sequencer and fetch mechanism may be considered the most basic elements of a microprocessor or computer as they are commonly exercised many times for the execution of each machine instruction. Accordingly, the additive effect of delays in the sequencer can significantly impact the performance of the processor or, in the case of a CPU, the overall system.
The most common prior art technique for minimizing the above described fetch delays is to prefetch using the next sequential microinstruction address before the test results become valid. If the selection is the correct choice, then no delay is incurred. If the choice is incorrect, the fetched microinstruction is ignored and the branch microinstruction is fetched. The incorrect choice results in an additional cycle time to fetch the correct microinstruction but it does not occur at each branch decision point. Some improvement in this basic technique has been provided by what has been referred to as "branch prediction strategies". One method is to utilize a bit in the test microinstruction to predict the most likely result. Therefore, instead of always fetching the next sequential microinstruction, the controller fetches the most likely next microinstruction and has a better than 50% chance of preselecting the correct path.
Another prior art technique is to prefetch both paths or sequences of microinstructions and store them in a buffer. Accordingly, when the test becomes valid, the next correct microinstruction is available without delay and the incorrect path is ignored. Hardware implementation of this technique may be found for example in the IBM 3033 architecture. The implementation of this technique heretofor has utilized very expensive dual ported memories so that both paths may be simultaneously fetched. Especially for use in mini-computer CPUs and microprocessors, the commercially available dual ported memories which provide simultaneous access of two addresses are prohibitively expensive.